Modern semiconductor devices are typically packed with a high density of transistors having minimum channel (gate) lengths. These devices generally exhibit short channel effects, which limit their performance. Transistors with longer channel lengths are designed to mitigate the short channel effects and off-current leakage. However, such designs typically require larger pitch size between transistors which compromises high die area utilization.
Recessed channel array transistors (RCATs) have been used where low leakage or low variation of current leakage is critical, such as in analog and memory devices. A RCAT demonstrates decreased short channel effects relative to conventional transistors having the same gate length. That is, a RCAT has a longer effective gate length and significantly lower sub-threshold slope (SS) and drain-induced barrier lowering (DIBL) voltages, hence lower off current leakage and a more controllable voltage variation.
FIG. 1 illustrates a semiconductor device 101 with a conventional complimentary metal-oxide semiconductor (CMOS) transistor and a RCAT. The device 101 includes a semiconductor substrate 103, a CMOS transistor region 105, and a RCAT region 107 separated from the CMOS transistor region by an isolation region 109. The CMOS transistor includes source/drain region 111, and the RCAT includes source/drain regions 113. The CMOS gate electrode 115 and the RCAT gate electrode 117 each include a conformal layer of a high-k dielectric material 119 and one or more layers of gate metals 121. Spacers 123 are formed on opposite sides of each of the two electrodes, and a dielectric layer 125 (serving as contact etch stop layer) and an inter-layer dielectric (ILD) 127 are formed over the substrate.
In comparison to the CMOS transistor, the RCAT has a longer path (channel length) between the source/drain regions and therefore, results in better suppression of short-channel effects. However, while RCATs are used in advanced dynamic random access memory (DRAM) devices, these are not as suitable for use in logic transistors and static random access memory (SRAM) devices due to larger threshold voltage (Vt) variations and damage on mobility caused by the methods used for their production, e.g., plasma etching, and variations of doping to the vertical channel.
The scaling of planar CMOS into 20 nm leads to growing variations of smallest transistors (usually used in SRAM arrays) and degradation in threshold voltage mismatch (Vtmm) and minimum voltage (Vmin) yield (due to fluctuations of process parameters such as critical dimensions (CD's), over-lay, random doping fluctuations, etching, and wet clean.
A need therefore exists for new methodology enabling fabrication of minimum size CMOS transistors having a longer effective channel (gate) length between the source/drain regions for suppression of short-channel effects and the resulting devices.